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# 15.5  Power Dissipation

Power dissipation in CMOS logic arises from the following sources:

• Dynamic power dissipation due to switching current from charging and discharging parasitic capacitance.
• Dynamic power dissipation due to short-circuit current when both n -channel and p -channel transistors are momentarily on at the same time.
• Static power dissipation due to leakage current and subthreshold current.

## 15.5.1 Switching Current

When the p -channel transistor in an inverter is charging a capacitance, C , at a frequency, f , the current through the transistor is C (d V /d t ). The power dissipation is thus CV (d V /d t ) for one-half the period of the input, t = 1/(2 f ). The power dissipated in the p -channel transistor is thus

 1/(2f) d V V DD Ú CV –– d t = Ú CV d V 0 d t 0 = 0.5 CV DD 2 (15.3)

When the n -channel transistor discharges the capacitor, the power dissipation is equal, making the total power dissipation

 P 1 = fCV 2 DD (15.4)

Most of the power dissipation in a CMOS ASIC arises from this source—the switching current. The best way to reduce power is to reduce V DD (because it appears as a squared term in Eq.  15.4 ), and to reduce C , the amount of capacitance we have to switch. A rough estimate is that 20 percent of the nodes switch (or toggle) in a circuit per clock cycle. To determine more accurately the power dissipation due to switching, we need to find out how many nodes toggle during typical circuit operation using a dynamic logic simulator. This requires input vectors that correspond to typical operation, which can be difficult to produce. Using a digital simulator also will not take into account the effect of glitches, which can be significant. Power simulators are usually a hybrid between SPICE transistor-level simulators and digital event-driven simulators [ Najm, 1994].

## 15.5.2 Short-Circuit Current

The short-circuit current or crowbar current can be particularly important for output drivers and large clock buffers. For a CMOS inverter (see Problem 15.17 ) the power dissipation due to the crowbar current is

 P 2 = (1/12) b f t rf (V DD – 2 V t n ) 3 (15.5)

where we assume the following: We ratio the p -channel and n -channel transistor sizes so that b = ( W/L ) m C ox is the same for both p - and n -channel transistors, the magnitude of the threshold voltages V t n are assumed equal for both transistor types, and t rf is the rise and fall time (assumed equal) of the input signal [ Veendrick, 1984]. For example, consider an output buffer that is capable of sinking 12 mA at an output voltage of 0.5 V. From Eq. 2.9 we can derive the transistor gain factor that we need as follows:

 I DS b = –––––––––––––––––––––––– (15.6) [( V GS – V t n ) -0.5 V DS ] V DS 12 ¥ 10 –3 = ––––––––––––––––––––––––– [(3.3 – 0.65) – (0.5) (0.5)] (0.5) = 0.01 AV –1

If the output buffer is switching at 100 MHz and the input rise time to the buffer is 2 ns, we can calculate the power dissipation due to short-circuit current as

 P 2 = (1/12) b f t rf (V DD – 2 V t n ) 3 (15.7) = (0.01) (100 ¥ 106) (2 ¥ 10 –9 ) (3.3 – (2)(0.65)) 3 = 0.00133W   or about 1 mW .

If the output load is 10 pF, the dissipation due to switching current is

 P 1 = fCV 2 DD = (100 ¥ 10 6 ) (10 ¥ 10 –12 )(3.3) 2 = 0.01089 W   or about 10 mW .

As a general rule, if we adjust the transistor sizes so that the rise times and fall times through a chain of logic are approximately equal (as they should be), the short-circuit current is typically less than 20 percent of the switching current.

For the example output buffer, we can make a rough estimate of the output-node switching time by assuming the buffer output drive current is constant at 12 mA. This current will cause the voltage on the output load capacitance to change between 3.3 V and 0 V at a constant slew rate d V /d t for a time

 C D V (10 ¥ 10 –12 ) (3.3) D t = ––––– = –––––––––––––––– (15.8) I (12 ¥ 10 –3 )

This is close to the input rise time of 2 ns. So our estimate of the short-circuit current being less than 20 percent of the switching current assuming equal input rise time and output rise time is valid in this case.

## 15.5.3  Subthreshold and Leakage Current

Despite the claim made in Section 2.1, a CMOS transistor is never completely off . For example, a typical specification for a 0.5 m m process for the subthreshold current (per micron of gate width for V GS = 0 V) is less than 5 pA m m –1 , but not zero. With 10 million transistors on a large chip and with each transistor 10 m m wide, we will have a total subthreshold current of 0.1 mA; high, but reasonable. The problem is that the subthreshold current does not scale with process technology.

When the gate-to-source voltage, V GS , of an MOS transistor is less than the threshold voltage, V t , the transistor conducts a very small subthreshold current in the subthreshold region

 Ê q V GS ˆ I DS = I 0 exp Á ––––– – 1 ˜ (15.9) Ë nkT ¯

where I 0 is a constant, and the constant, n, is normally between 1 and 2.

The slope, S, of the transistor current in the subthreshold region is

 –nkT nkT S = –––– log 10 e = 2.3 –––– V/decade . (15.10) q q

For example, at a junction temperature, T = 125 °C ( ª 400 K) and assuming n ª 1.5, S = 120 mV/decade ( q = 1.6 ¥ 10 –19 Fm –1 , k = 1.38 ¥ 10 –23 JK –1 ), which does not scale. The constant value of S = 120 mV/decade means it takes 120 mV to reduce the subthreshold current by a factor of 10 in any process. If we reduce the threshold voltages to 0.36 V in a deep-submicron process, for example, this means at V GS = 0 V we can only reduce I DS to 0.001 times its value at V GS = V t . This problem can lead to large static currents.

Transistor leakage is caused by the fact that a reverse-biased diode conducts a very small leakage current. The sources and drains of every transistor, as well as the junctions between the wells and substrate, form parasitic diodes. The parasitic-diode leakage currents are strongly dependent on the type and quality of the process as well as temperature. The parasitic diodes have two components in parallel: an area diode and a perimeter diode. The ideal parasitic diode currents are given by the following equation:

 Ê q V D ˆ I = I s exp Á ––––– – 1 ˜ (15.11) Ë nkT ¯ .(15.1)

Table 15.6 shows specified maximum leakage currents of junction parasitic diodes as well as the leakage currents of the field transistors (the parasitic MOS transistors formed when poly crosses over the thick oxide, or field oxide) in a typical 0.5 m m process.

 TABLE 15.6  Diffusion leakage currents (at 25 °C) for a typical 0.5 m m ( l = 0.25 m m) CMOS process. Junction Diode type Leakage (max.) Unit n -diffusion/ p -substrate area 0.6 fA m m –2 V –1 n -diffusion/ p -substrate perimeter 2.0 fA m m –1 V –1 p -diffusion/ n -well area 0.6 fA m m –2 V –1 p -diff/ n -well perimeter 3.0 fA m m –1 V –1 n -well / p -substrate area 1.0 fA m m –2 V –1 Field NMOS transistor 100 fA m m –1 Field PMOS transistor 30 fA m m –1

For example, if we have an n -diffusion region at a potential of 3.3 V that is 10 m m by 4 m m in size, the parasitic leakage current due to the area diode would be

 40 m m 2 ¥ 3.3 V ¥ 0.6 fA m m –2 V –1 = (40) (3.3) (0.6 ¥ 10 –15 ) = 7.92 ¥ 10 –14 A ,

or approximately 80 fA.

The perimeter of this drain region is 28 m m, so that the leakage current due to the perimeter diode is

 28 m m ¥ 3.3 V ¥ 2.0 fA m m –1 V –1 = (28) (3.3) (2.0 ¥ 10 –15 ) = 2.848 ¥ 10 –13 A ,

or approximately 0.2 pA, over twice as large as the area-diode leakage current.

As a very rough estimate, if we have 100,000 transistors each with a source and a drain 10 m m by 4 m m, and half of them are biased at 3.3 V, then the total leakage current would be

 (100 ¥ 10 5 ) (2) (0.5) (280 ¥ 10 –15 ) = 2.8 ¥ 10 –6 A , (15.12)

or approximately 3 m A. This is the same order of magnitude (a few microamperes) as the quiescent leakage current, I DDQ , that we expect to measure when we test an ASIC with power applied, but with no signal activity. A measurement of more current than this in a nonactive CMOS ASIC indicates a problem with the chip manufacture or the design. We use this measurement to test an ASIC using an IDDQ test.