by Donnamaie E. White

Which Array Technology?

The broad categories of technologies are CMOS, BiPOLAR, BiCMOS, and GaAs. Figure 1-4 provides a family tree of the most common technologies, at least at this moment. Array technology is a subject in itself and the reader is referred elsewhere for detailed discussions on any specific process.

Figure 1-4a The Dominant Technologies

Bipolar as used in conjunction with arrays in this text refers to ECL-internal with TTL, ECL 10K, ECL 100K I/O modes, or mixed ECL/TTL interface capability. Not all arrays offer the ability to mix TTL and ECL or to mix ECL 10K and ECL 100K on one chip. Some arrays may limit the types of macros that can be placed on the I/O cells. Design limits imposed by these restrictions are generally based on the array technology.

The AMCC BiCMOS has the same interface capability as the bipolar arrays while providing a CMOS internal core. BiCMOS interfaces include CMOS, TTL, ECL 10K and ECL 100K and combinations of all. Not all BiCMOS arrays offer the ability to mix TTL and ECL or ECL 10K and ECL 100K on one chip.

Figure 1-4b Relations among Silicon Technologies

Technology differences for VLSI are primarily speed and power. CMOS is lower speed, lower power. Bipolar at 600MHz or 1.2GHz and up is faster with a high power dissipation (5-7, up to 16 watts for the fastest arrays is not unusual). BiCMOS is intended to be a combination of these two, providing a reasonable speed (about 130MHz and up) at greatly reduced power dissipation.

The actual maximum frequency of operation and the power dissipation will vary from series to series even within the technologies. Data sheets for the array series of interest should be reviewed and compared as a first method of estimation for applicability.

Note: One array series may be lower power at one frequency and higher power at another. Comparisons must be made using equivalent conditions. When the conditions are not specified, ask! All vendors maintain Field-Application Engineers that can explain how measurements were taken or what assumptions were used.

Figure 1-4c Relations among Technologies