Rambus Validates Interoperability of DDR4 High-performance Memory IP Solution for Arm-based Datacenter Systems

Rambus DDR4 3200 PHY, Arm CoreLink Dynamic Memory Controller provide comprehensive solution for datacenter and communications

SUNNYVALE, Calif. — (BUSINESS WIRE) — October 19, 2017Rambus Inc. (NASDAQ: RMBS) today announced the validated interoperability of the Rambus DDR4 PHY and the Arm® CoreLink DMC-620 Dynamic Memory Controller. Together, these IP blocks offer speeds of up to 3200 Mbps, the highest performance memory speed available on the market. This partnership provides a verified solution to chip designers, reducing design time and improving time-to-market for demanding datacenter and communications applications.

“With rising chip design and IP integration costs, these pre-validated solutions from Rambus and Arm provide customers with an easy path to implementation and the peace of mind of a proven solution,” said Hemant Dhulla, vice president of product of Rambus Memory and Interfaces Division. “Rambus strives to work with companies like Arm that are leaders in the IP ecosystem to deliver high-quality, comprehensive solutions to the market.”

The CoreLink DMC-620 Dynamic Memory Controller is a fast, single-port Coherent Hub Interface (CHI) for transferring data from its CoreLink CMN-600 (Coherent Mesh Network) to the Rambus DDR4 memory PHY. CoreLink DMC-620 offers a combination of benefits to power, cost, and performance and guarantees interoperability with the Rambus DDR4 PHY, proven at speeds up to 3200 Mbps.

“Design teams face complex challenges in scaling the number of computing cores for advanced datacenter SoCs, while minimizing integration and testing time to ensure faster time-to-market,” said Jeff Defilippi, senior product manager, Infrastructure Business Unit, Arm. “Our collaboration with Rambus removes another degree of difficulty in designing purpose-built SoCs, resulting in higher-performing systems built for the most demanding cloud and enterprise workloads.”

The Rambus DDR4 memory PHY and CoreLink DMC-620 are both DFI 4.0 compliant, allowing the PHY and memory controller to interoperate. The Rambus memory PHY is fully JEDEC compliant to the DDR4 and DDR3/3L/3U standards. The Rambus silicon-proven PHY combines performance and power efficiency with superior design flexibility to provide customers with a differentiated and easy to integrate solution. For additional information on Rambus DDR4 PHY solutions, please visit rambus.com/ddrnphys.

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About Rambus Memory and Interfaces Division

The Rambus Memory and Interfaces Division develops products and services that solve the power, performance, and capacity challenges of the communications and data center computing markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include chips, architectures, memory and SerDes interfaces, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus products deliver improved time-to-market and first-time-right quality.

About Rambus Inc.

Rambus creates innovative hardware and software technologies, driving advancements from the data center to the mobile edge. Our chips, customizable IP cores, architecture licenses, tools, software, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile payments, and smart ticketing. At Rambus, we are makers of better. For more information, visit rambus.com.

Source: Rambus Inc.



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