MathWorks Automates Vision Systems Design for Implementation on FPGAs and ASICs

Vision HDL Toolbox automatically generates FPGA-proven code for frame sizes up to 8k resolution and for high-frame-rate video

NATICK, Mass. — (BUSINESS WIRE) — February 26, 2020MathWorks today announced that with the recent availability of Release 2019b of the MATLAB and Simulink product families, Vision HDL Toolbox includes native multipixel streaming support to process high-frame-rate (HFR) and high-resolution videos on FPGAs. Video, image processing, and FPGA design engineers can speed the exploration and simulation of behavior and implementation tradeoffs when processing 4k or 8k video and videos with resolutions of 240fps or higher.

Engineers designing FPGAs for real-time processing of high-resolution and HFR video in applications such as industrial inspection, medical imaging, and intelligence, surveillance, and reconnaissance (ISR) are challenged to meet throughput, resource usage, and power consumption targets. Vision HDL Toolbox offers blocks that can process 4 or 8 pixels in parallel, with the underlying hardware implementation automatically updated to support simulation and code generation with the specified parallelism. This capability helps hardware engineers collaborate with image and video processing engineers to explore and simulate vision processing hardware behavior at a high level of abstraction. By adding HDL Coder to this design workflow, engineers can generate synthesizable, optimized target-independent VHDL or Verilog code directly from their verified high-level models.

“Implementing vision processing algorithms on FPGA, ASIC, and SoC devices requires clever tradeoffs between throughput and resource usage, and 4k, 8k, and high-frame rate video multiplies this challenge,” said Jack Erickson, principal product marketing manager at MathWorks. “Exploring the solution space and simulating at a high level of abstraction helps engineers converge more rapidly on an architecture before committing to Register-Transfer Level (RTL). Vision HDL Toolbox and its native multi-pixel-per-clock processing automatically implement all the details so engineers can focus on developing hardware-ready algorithms that meet their requirements.”

Vision HDL Toolbox provides pixel-streaming algorithms for the design and implementation of vision systems on FPGA, ASIC, and SoC devices. It provides a design framework that supports a diverse set of interface types, frame sizes, and frame rates. The video and image processing algorithms in the toolbox model hardware implementations that include latency, control signals, and line buffers.

The toolbox algorithms are designed to generate readable, synthesizable code in VHDL and Verilog (with HDL Coder). The generated HDL code is FPGA-proven for frame sizes up to 8k resolution and for HFR video.

Vision HDL Toolbox R2019b is available immediately worldwide. To learn more, visit:

About MathWorks
MathWorks is the leading developer of mathematical computing software. MATLAB, the language of engineers and scientists, is a programming environment for algorithm development, data analysis, visualization, and numeric computation. Simulink is a block diagram environment for simulation and Model-Based Design of multidomain and embedded engineering systems. Engineers and scientists worldwide rely on these product families to accelerate the pace of discovery, innovation, and development in automotive, aerospace, electronics, financial services, biotech-pharmaceutical, and other industries. MATLAB and Simulink are also fundamental teaching and research tools in the world’s universities and learning institutions. Founded in 1984, MathWorks employs more than 4500 people in 16 countries, with headquarters in Natick, Massachusetts, USA. For additional information, visit

MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See for a list of additional trademarks. Other product or brand names may be trademarks or registered trademarks of their respective holders.


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