Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

Clock input

The clock input will use IE34H, a differential high-speed input with a Y and YN output. For CML-compatible input, use IE31H. The clock will have two loads. It uses two I/O cells and two pads. The clock is in the critical path.

Other options that could be considered include the use of the driver version of the differential input, IE32D. The driver handles 32 loads and has k-factors with less skew than those of the H-option IE34H. If the IE34H proves to be too slow or the inter-macro delays too long, the IE32D would be the choice for a speed upgrade. The driver is shown in Figure A-5.

Figure A-5 Differential Input Macro

ECL outputs - first pass

All outputs in the initial version of the circuit were the OE42S, a cut-off (ECL output with an enable) macro used with the enable tied low (always on) except for the two controlled outputs. (This macro was the only 50 ohm non-Darlington termination in the initial release of the library.) The (111) version of the library added OE11S, a NOR-input 50 ohm termination, rated for 350MHz. The other option is to have a custom 50 ohm macro created, not worth the effort for the case study but something that should be reviewed in a real circuit where power and cell space are at a premium.

The OE42S enable is tied low by way of the GT87D static driver, a macro that supplies steady HIGH and LOW signals when unused macro pins cannot be "clipped" low or allowed to float.

There will be 64 data output for the pipeline, six outputs for the pass-through signals, two MUX outputs and an output for the parametric gate tree for a total of 73 outputs. Each OE42S uses one I/O cell and one pad.

The fan-out load limit for the GT87D is 50 loads so two will be required to supply the OE42S enable pins in this first version of the design. The basic module is shown in Figure A-6.

Note that the OE11S is easier to use and uses less power - reasons to consider challenging the initial solution.

Figure A-6 Macro Design Restrictions

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com