Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

SOLUTION - Q20000

Check for I/O mode and power supply.

This is a 100% ECL circuit and uses no Darlingtons so that a single -5.2V supply is allowed.

The AMCC chip macro is Q20080ECL10K, which sets the I/O mode at 100% ECL with ECL 10K/KH inputs. The power supply parameter is set at STD5 for standard reference -5.2V supply. The product grade parameter is set at MIL for military. Between them, these parameters define this circuit as a MIL5 circuit, using the MIL5 library and annotation data. The chip macro is shown in Figure A-2.

Figure A-2 AMCC Icon for the Chip Macro

Selecting a flip/flop - first pass

The need for a master reset will reduce the set of available flip/flop macros that could be used to those with a synchronous or asynchronous reset (or set). The use of a 2:1 MUX - flip/flop combination will further reduce the choices for the first stage of the circuit.

For the chosen Q20000 macro library, FF46S is a D flip/flop with a 2:1 MUX on the data input and an asynchronous reset. It is more silicon-efficient to use a combination MUX-F/F macro than to implement the design with individual multiplexor and flip/flop macros.

The second stage flip/flop needs a reset and at this stage in the design process needs both Q and QN outputs. FF10S was chosen as the appropriate macro. See Figure A-3.

Figure A-3 MUX and two F/Fs in Two Macros

Selecting the ECL input

All inputs (reset, selects, output enables and data) except the clock will use the IE93S, a simple buffered input that produces both Y and YN outputs shown in Figure A-4. The YN output will be used to input to the gate tree to keep loading off the Y path. To reduce power, the IE94 version with only the Y output could have been chosen. This option would use three loads on the Y path, two to the main circuit (register input and 16:1 MUX input) and one to the parametric tree.

Figure A-4 Output Macro with Complementary Outputs

For this circuit, the saving of one load is not significant in that the loads are not in the critical path. In another instance, the reduction of one load could be the difference between meeting or failing specification.

There are 64 data inputs, 32 dataA and 32 dataB, plus one select for the input 2:1 MUX, and four for the 16:1 MUX controls (and four 16:1 MUXs) for a total of 82 IE93S macros. Each macro uses one I/O cell and one pad. (See Table A-1.)

Table A-1 Required IE93S Inputs

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com