Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

Parity tree

A parity tree of all inputs (required for parametric VIL, VIH testing) can be formed from NOR gates using the GT60L or GT60S, an 8-input NOR macro. The L-option is slower and uses less power. The speed of the gate tree is not important since testing is functional at 100ns intervals. The first estimate for the tree is to use eleven GT60S macros in a three-level structure to accommodate the 79 input signals. (The 78 data signals plus the clock are required.) The parity tree is shown in Figure A-8.

Figure A-8 Parity Tree

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com