Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

FAN-OUT LOADS

The final step toward an estimate of circuit size requires that fan-out loads be examined. Most macros in the Q2000 library will have a fan-in of one except for H-option macros that will have a higher fan-in (and larger cell size). This is not always the case but should be considered when examining macro options.

Select lines for 16:1 MUX

Select lines to each 16:1 have at most four loads. No buffering is required for the IE93S macros that can drive 18 loads each.

Select lines to 2:1 MUX structure

The select to the 2:1 MUX structure has 32 loads and will need buffering. One macro can drive 18 loads, adding a gate buffer tree such as two GT09S macros allows one primary input to drive 32 loads. (See Figure A-10.)

Figure A-10 Buffer Tree for the 2:1 MUX (32 Loads)

The other option is to switch the IE93S for an IE23D driver that can drive 32 loads directly. The IE23D driver uses twice as much current as an IE93S macro but would save the internal cells that the GT09S macros would have used.

Reset loading

RESET requires the same decision process. In this case, the signal goes to 64 flip/flops. The AR pin for the FF46S is two loads and the AR pin for the FF10S is 1 load for a total of 96 loads. Either six GT09S macros or three GT55D macros can provide the drive. The GT55D driver uses twice as much current as a GT09S macro and is twice as large. Since half as many are required, on comparing cell usage and power these two solutions are equivalent.

On the schematic, eight GT09S macros were used to simplify the schematic design (eight pages are replicated). (See Figure A-11.)

Figure A-11 Reset Signal Buffer Tree

RESET STRUCTURE - ONE OPTION

Reset structures are often treated as clock structures without the need for speed. This structure is only one level in depth. Current synthesis systems will create the necessary buffer trees to support the load being driven.

Clock

The clock is handled differently since all clock nets must be derated. There are 64 loads from the flip/flops, plus 1 load due to the parametric gate tree, for a total of 65 loads. The IE31H can drive 10 loads with a 40% derating. The GT55D driver, derated, drives 19 loads and presents a fan-in load of two to the driving macro. Four GT55D macros would provide the drive capability with full 40% derating down the path as shown in Figure A-12.

Figure A-12 Clock Tree

CLOCK STRUCTURE - ONE OPTION

Derating guidelines are part of the array design rules. Macro load limits are listed in the macro documentation.

Place & Route software today creates the clock tree structure based on the commands in a control script. The commands involve suggested buffer or macro to be used and clock tree depth. In the near future, Floorplanners will incorporate this function. Clock trees have priority during layout, depending on the design constraints supplied to the Place&Route tool.

When the clock tree is to be constructed by the Place&Route software, all timing analysis prior to the routing is done using a modeled clock, approximating what the final clock tree behavior might be.

Static Driver

The static driver required to drive the always-on output enable inputs can handle 50 loads but 64 are required in this version of the design. Two GT87D macros can be used. One is shown in Figure A-13.

Figure A-13 Static Driver

Static driver is not a term that shows up in macro lists today. Rather, high-drive options on various macros are used. If no one macro can handle the load to be driven, then a buffer tree is constructed by the synthesis tool.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com