Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Case Study: Sizing A Design

Last Edit July 22, 2001

REVIEW OF SIZE - SECOND PASS

The revised estimate (one version of the solution) shows the circuit requirements as they are now understood.

Table A-3 Second Sizing Estimates

TOTAL L CELLS REQUIRED 267

Change OE42S to OE11S and delete the 2 GT87Ds.

This fits into the Q20080 array that has 162 I/O cells and 2044 L cells. This is a severely I/O-bound design (of course!). A design is either core-limited or I/O limited.

Note: When vectors are written for this array, they should be designed so that no more than 16-32 of the outputs switch at any one time. These are AMCC-specific vector design rules.

Table A-4 AMCCERC Population ERC

PACKAGE SIZE

The minimum number of signal pins that should be available on a package for this circuit is 157 (162 signals plus the 4 fixed signals minus the 9 added grounds). The worst-case number of signal pins that could be required on a package for this circuit is 166 (162 signals plus the 4 fixed signals). The truth is in the middle and is placement-dependent.

PROBLEMS

• The OE42S is limited to a toggle frequency of 350MHz. If the clock is running at 500MHz, the outputs could be toggling slower. If not, then the OE42S is not a correct choice if speed is to be maintained. Neither is the OE11S!
  
  
• Insufficient added grounds is not a minor problem.
  
  
• The circuit uses nearly 8 Watts - much too high.

ALTERNATIVE SOLUTION

The differential output OE14S could be used in place of two OE42S macros and the GT87D driver (at least one) could be deleted. This reduces the OE42S macros from 73 to 9, and the 7 always-on enables could be driven by a GT08L NOR gate instead of a static driver macro.

The use of OE14S provides a cleaner solution (less skew) plus it frees internal cells. The maximum frequency of the OE14S is 1.2GHz. One output pad can be used as the true signal and the other as the compliment.

Another advantage is the reduced requirement for added grounds. The 32 differential outputs count as 32 outputs and not as 64, reducing the re-quirement for this group to 8 added IEVCC, what was provided. The ninth IEVCC applies to the miscellaneous other outputs. There will be a warning issued by AMCCERC that there might not be sufficient added grounds for these miscellaneous outputs - the algorithm defined by AMCC requires that two IEVCC macros be added.

POWER

The DC power dissipation for the maximum worst-case MILITARY DC power for the OE42S version of the circuit was estimated to be over 8 Watts.

The DC power computation for the OE14S version, same conditions, is esti-mated to be 5.88 Watts. (This number is based on the circuit as shown in the schematics and the February 1991 library specifications.)

Reducing the GT08S macros to GT08L macros can further reduce power.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com