Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix: Case Study in Sizing a Design
  • Target Array: AMCC Q20080 (1994 Data)
  • Solution - Q20000
  • Selecting a Flip/Flop - First Pass
  • Selecting the ECL Output
  • Clock Input
  • 16:1 MUX
  • Parity Tree
  • Review Status so far
  • Exercise
  • Simultaneouly Switching Outputs
  • Fanout Loads
    • Select Lines for 16:1 MUX
    • Reset Loading
    • Clock
    • Static Driver
  • Review of Size - Second Pass
  • Package Size
  • Problems
  • Alternative Solution
  • Power
  • Further Thought
  • The Schematics
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Last Edit July 22, 2001

Architectural Specification or Hardware Specification

Once a clear definition exists of the circuit or circuits that will be placed on one array, then the planned design can be developed. This is on a smaller module scale than the block-level functional specification, e.g., at the level of counters, adders, latches, registers, sequencers, etc. The performance requirements defined in the functional specification can be used to select the technology.

Table 3-5 Array-Specific Specifications

The review of available arrays is conducted in parallel with the creation of the hardware specification.

With the descriptions developed for the modules, equivalent gate estimates can be made for the circuit, or estimated cell usages can be computed for the circuit on a specific array. The array vendor Applications Engineer can help with the sizing esti mate.

The hardware design specification details what the designer intends to do to meet the target functional specification. This level of specification can be equated to a PDL (program definition language) description of software and is the basis for the evolution of HDL, hardware description language, and its derivatives.

If a particular testing methodology is being enforced, the sizing estimates must take this additional logic into account. If additional testing logic, such a parametric gate tree or parity logic, is to be used, it must be included in the sizing estimates.

The specification may include proposed vendors and arrays.

Table 3-6 Components of The Hardware Specification

There should be a design review of the architectural or hardware specification before final selection of an array series. On final selection, the specification should be revised to show that series and all computations performed for that series.

Note that a workstation can provide some assistance. The critical path may be captured in more than one version and comparisons made based on an annotated simulation.

Power and sizing details can be run against a macro list rather than a full interconnect netlist. (This tool is vendor-dependent.) Check if such a pre-capture tool is available to help size the circuit.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com